The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of improving memory bandwidth utilization in systems that include isochronous data streams.
An important function of computer systems is that of processing isochronous data streams. Isochronous data streams are those data streams that have strict throughput and latency requirements. An example of one such data stream is a data stream for a video display device. Video display devices require a certain amount of data every fixed period. If the required data is not delivered to the video display device at the required rate and within the required time period, then some form of display corruption will result.
Isochronous data streams typically have very even data consumption rates, that is, for a given period of time, the amount of data consumed will always be the same. Memory access, on the other hand, is typically very uneven due to arbitration with other data streams. For example, when a video display device requires data it must arbitrate for access to memory with other system resources. The result is uneven and unpredictable access to memory. Another issue with isochronous data streams is that an isochronous data stream is likely to operate at a different clock frequency than that of the memory subsystem. These two issues can be solved by using an intermediate storage first-in, first-out buffer (FIFO). The FIFO can accept data from memory at whatever rate the memory can deliver the data and the FIFO can output data at the rate required by the isochronous data stream.
The FIFO technique works so long as the FIFO is never allowed to go empty. If the FIFO goes empty at any point, the isochronous data stream will be corrupted. To help prevent this situation, isochronous data streams are typically assigned the highest priority for arbitrating access to memory.
In order to maximize memory efficiency, the requests for data are typically made as large as possible. Because for an isochronous data stream the memory access latency, memory data rate, FIFO size, and FIFO drain rate are known, a maximum request size can be calculated as well as the FIFO data level at which the request must occur. This data level may be referred to as a xe2x80x9cwatermarkxe2x80x9d. When the data level of the FIFO falls below the watermark level, a request is made to a memory arbiter for access to memory. Typically, this request will be allowed to interrupt other ongoing memory transactions in order to ensure that the FIFO receives data within the required time. While the technique of allowing the isochronous data stream memory request to interrupt other memory transactions ensures that the isochronous data stream receives data at a satisfactory rate, the interruptions result in latency penalties for other computer system functions and overall computer system performance is negatively affected.